Field of the Invention
The present invention relates to a thin-film transistor array and in particular to a thin-film transistor array suitable for flexible substrates or printing methods.
Discussion of the Background
Thin-film transistor (TFT) arrays of amorphous silicon (a-Si) or polysilicon (poly-Si) are fabricated on the basis of the technique of fabricating transistors or integrated circuits having semiconductors as substrates. Such TFT arrays are applied to liquid crystal displays, electrophoretic displays or the like. When a TFT, which plays the role of a switch, is turned on by a selected voltage applied to the gate wiring, a signal voltage supplied to the source wiring is applied to a pixel electrode connected to the drain. The applied voltage is retained in a storage capacitor configured by a pixel electrode, a gate insulator film and a capacitor electrode. The voltage from the capacitor wiring is applied to capacitor electrode. In the case of a TFT array, the functions of the source and the drain depend on the polarity to be applied to. Therefore, source and drain cannot be named by the characteristics of the functions. For convenience herein, one terminal is termed as a source and the other terminal is termed as a drain throughout the specification. In the present invention, the terminal connected to a wiring is referred to as a source and the terminal connected to a pixel electrode is referred to as a drain.
When thin-film transistor arrays are used as display elements, short circuits or disconnections in a wiring can cause line defects or point defects. In this regard, some methods are proposed to reduce the influence of the defects or to correct the defects.
PTL 1 discloses that cross-bridges 31 are added to the source wirings 4′ to form a ladder pattern to eliminate the influence of disconnections in the source wirings 4′ (FIG. 19). However, this disclosure makes no mention of how the short circuit defects are corrected.
PTL 2 discloses a transistor array that includes two TFTs per pixel (FIG. 20). When one of the two TFTs causes a short circuit between its source electrode 4 and drain electrode 5, the TFT in question is cut off by using a laser to reduce the influence of the short circuit. In this case, however, there are problems that the on-state current is reduced to half and the gate feedthrough voltage is reduced.
The problem that the on-state current is reduced to half causes no influence if the transistor array is overdesigned such that one TFT can suffice. If the transistor array is not overdesigned, the shortage of the on-state current leads to insufficient voltage.
Reducing the number of TFTs to one will also reduce the gate-drain capacity to the capacity of one TFT. Therefore, use of only one TFT reduces the gate feedthrough voltage that causes pixel potential change when the gate potential is turned off. When the gate feedthrough voltage is not negligible, the gate feedthrough voltage is required to be cancelled. To this end, the reference potential of a counter electrode is offset by an amount equivalent to the gate feedthrough voltage. However, the offset has to be performed on the premise that the gate feedthrough voltages of all the pixels are equal. With a pixel in which one of the TFTs is cut off, the gate feedthrough voltage is reduce to substantially half. Accordingly, about a half of the gate feedthrough voltage is constantly applied across the counter electrode and the pixel, creating a problem of causing a slight change in display in the case of an electrophoretic display. In the case of a liquid crystal display, there is a problem that DC components are applied to the liquid crystal and seizing is likely to occur.
Further, there is no mention of a way of coping with a short circuit or the like occurring in portions such as between a source wiring and a pixel electrode, other than a portion between a source electrode and a drain electrode.
PLT 1: JP-A-H10-133228
PLT 2: JP-A-H07-199221